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| ML145146 4-Bit Data Bus Input PLL Frequency Synthesizer INTERFACES WITH DUAL-MODULUS PRESCALERS Legacy Device: Motorola MC145146-2 The ML145146 is programmed by a 4-bit input, with strobe and address lines. The device features consist of a reference oscillator, 12-bit programmable reference divider, digital phase detector, 10-bit programmable divide-by-N counter, 7-bit divide-by-A counter, and the necessary latch circuitry for accepting the 4-bit input data. * Operating Temperature Range: TA - 40 to +85C * Low Power Consumption Through the Use of CMOS Technology * 3.0 to 9.0 V Supply Range * Programmable Reference Divider for Values Between 3 and 4095 * Dual-Modulus 4-Bit Data Bus Programming * / N Range = 3 to 1023, / A Range= 0 to 127 * "Linearized" Digital Phase Detector Enhances Transfer Function Linearity * Two Error Signal Options: Single-Ended (Three-State) Double-Ended P DIP 20 = RP PLASTIC DIP CASE 738 1 20 20 SOG 20 W = -6P SOG PACKAGE CASE 751D 1 CROSS REFERENCE/ORDERING INFORMATION PACKAGE MOTOROLA LANSDALE P DIP 20 MC145146P2 ML145146RP SOG 20W MC145146DW2 ML145146-6P Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE. PIN ASSIGNMENT D1 D0 fin 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 D2 D3 fR R V fV MC LD ST A2 BLOCK DIAGRAM VSS PDout OSCin OSCout D0 D1 D2 D3 A2 A1 A0 ST 12-BIT / R COUNTER L5 L6 L7 LOCK DETECT VDD fR OSCin OSCout LD A0 A1 PHASE DETECTOR A PDout fV LATCH CONTROL CIRCUITRY LATCHES L2 fin L3 L4 L0 L1 PHASE DETECTOR B V R 10-BIT / N COUNTER 7-BIT / A COUNTER CONTROL LOGIC MODULUS CONTROL (MC) Page 1 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. Page 2 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. Page 3 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. Page 4 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. Page 5 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. PIN DESCRIPTIONS INPUT PINS D0 - D3 Data Inputs (Pins 2, 1, 20, 19) Information at these inputs is transferred to the internal latches when the ST input is in the high state. D3 (Pin 19) is the most significant bit. f in Frequency Input (Pin 3) Input to /N portion of synthesizer f in is typically derived from loop VCO and is AC coupled into Pin 3. For larger amplitude signals (standard CMOS - logic levels) DC coupling may be used. OSCin/OSCout Reference Oscillator Input/Output (Pins 7 and 8) These pins form an on-chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSCin to ground and OSCout to ground. OSCin may also serve as input for an externally-generated reference signal. This signal is typically AC coupled to OSCin, but for larger amplitude signals (standard CMOS-logic levels) DC coupling may also be used. In the external reference mode, no connection is required to OSCout. A0 - A2 Address Inputs (Pins 9, 10, 11) A0, A1 and A2 are used to define which latch receives the information on the data input lines. The addresses refer to the following latches. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Selected Latch 0 Latch 1 Latch 2 Latch 3 Latch 4 Latch 5 Latch 6 Latch 7 Function / A Bits / A Bits / N Bits / N Bits / N Bits Reference Bits Reference Bits Reference Bits D0 0 4 0 4 8 0 4 8 D1 1 5 1 5 9 1 5 9 D2 2 6 2 5 -- 2 6 10 D3 3 -- 3 7 -- 3 7 11 ST Strobe Transfer (Pin 12) The rising edge of strobe transfers data into the addressed latch. The falling edge of strobe latches data into the latch. This pin should normally be held low to avoid loading latches with invalid data. OUTPUT PINS PDout Single-ended Phase Detector Output (Pin 5) Three-state output of phase detector for use as loop error signal. Frequency fV>fR or fV Leading: Negative Pulses Frequency fV LD Lock Detector (Pin 13) High level when loop is locked (fR, fV of same phase and frequency). Pulses low when loop is out of lock. MC Modulus Control (Pin 14) Signal generated by the on-chip control logic circuitry for controlling an external dual-modulus prescaler. The modulus control level is low at beginning of a count cycle and remains low until the /A counter has counted down from its programmed value. At this time, modulus control goes high and remains high until the /N counter has counted the rest of the way down from its programmed value (N - A additional counter since both /N and /A are counting down during the first portion of the cycle). Modulus control is then set back low, the counters preset to their respective programmed values, and the above sequence repeated. This provides for a total programmable divide value (NT) = N * P / A where P and P / 1 represent the dual-modulus prescaler divide values respectively for high and low modulus control levels. N the number programmed into the /N counter and A the number programmed into the /A counter. fV /N Counter Output (Pin 15) This pin is the output of the /N counter that is internallly connected to the phase detector input. With this output available, the /N counter can be used independently. V, R Phase Detector Outpiuts (Pins 16 adn 17) These phase detector outputs can be combined externally for a loop error signal. A single-ended output is also available for this purpose (see PDout). If frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by V pulsing low R remains essentially high. If the frequency fV is less than fR or if the phase of fV is lagging, then error information is provided by R pulsing low V remains essentially high. If the frequency of fV = fR and both are in phase, then both V and R remain high except for a small minimum time period when both pulse low in phase. fR /R Counter Output (Pin 18) This is the output of the / R counter that is internally connected to the phase detector input. With this output available, the / R counter can be used independently. POWER SUPPLY PINS VSS Ground (Pin 4) Circuit Ground VDD Positive Power Supply (Pin 6) The positive supply voltage may range from 3.0 to 9.0 V with respect to VSS. www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. Page 7 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. DESIGN CONSIDERATIONS CRYSTAL OSCILLATOR CONSIDERATIONS The following options may be considered to provide a reference frequency to Motorola's CMOS frequency synthesizers. The most desirable is discussed first. Use of a Hybrid Crystal Oscillator Commercially available temperature-compensated crystal oscillators (TCXOs) or crystal-controlled data clock oscillators provide very stable reference frequencies. An oscillator capable of sinking and sourcing 50 A at CMOS logic levels may be direct or DC coupled to OSCin. In general, the highest frequency capability is obtained utilizing a direct coupled square wave having a rail-to-rail (VDD to VSS) voltage swing. If the oscillator does not have CMOS logic levels on the outputs, capacitive or AC coupling of OSCin may be used. OSCout, an unbuffered output, should be left floating. For additional information about TCXOs and data clock oscillators, please consult the latest version of the eem Electronic Engineers Master Catalog, the Gold Book, or similar publications. Design an Off-Chip Reference The user may design and off-chip crystal oscillator using ICs specifically developed for crystal oscillator applications, such as the ML12061 MECL device. The reference signal from the MECL device is AC coupled to OSCin. For large amplitude signals (standard CMOS logic levels), DC coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest frequency capability is obtained with a direct-coupled square wave having rail-to-rail voltage swing. Use of the On-Chip Oscillator Circuitry The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source frequency. A fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in Figure 8. For VDD = 5.0 V the crystal should be specified for a load, ing capacitance. CL, which does not exceed 32 pF for frequencies to approximately 8.0 MHz, 20 pF for frequencies in the area of 8.0 to 15 MHz, and 10 pF for higher frequencies. These are guidelines that provide a reasonable compromise between IC capacitance, drive capability, swamping variations stray in IC input/output capacitance, and realistic CL values. The shunt load capacitance, CL, presented across the crystal can be estimated to be: The oscillator can be "trimmed" on-frequency by making a portion or all of C1 variable. The crystal and associated components must be located as close as possible to the OSCin and OSCout pins to minimize distortion, stray capacitance, stray inductance, and startup stabilization time. In some cases, stray capacitance should be added to the value for Cin and Cout. Power is dissipated in the effective series resistance of the crystal, Re. In Figure 10 The drive level specified by the crystal manufacturer is the maximum stress that a crystal can withstand without damaging or excessive shift in frequency. R1 in Figure 8 limits the drive level. The use of R1 may not be necessary in some cases (i.e. R1 = 0 ohms). To verify that the maximum DC supply voltage does not overdrive the crystal, monitor the output frequency as a function of voltage at OSCout. (care should be taken to minimize loading.) the frequency should increase very slightly as the dc supply voltage is increased. An overdriven crystal will decrease in frequency or become unstable with an increase in supply voltage. The operating supply voltage must be reduced or R1 must be increased in value if the overdrive condition exists. The user should note that the oscillator start-up time is proportional to the value of R1. Through the process of supplying crystals for use with CMOS inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals. Discussions with such manufacturers can prove very helpful. See Table 1. where Cin = 5.0pF (See Figure 9) Cout = 6.0pF (See Figure 9) Ca = 1.0pF (See Figure 9) CO = the crystal's holder capacitance (See Figure 10) C1 and C2 = external capacitors (See Figure 8) Page 8 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. RECOMMENDED READING Technical Note TN-24 Statek Corp. Technical Note TN-7 Statek Corp. E. Hafner, "The Piezoelectric Crystal Unit - Definitions and Method of Measurement", Proc. iEEE, Vol 57, No 2 Feb, 1969 D. Kemper, L. Rosine, "Quartz Crystals for Frequency Control", Electro-Tecchnology, June 1969 P.J. Ottowitz, "AGuide to Crystal Selection", Electronic Design, May 1966 DUAL-MODULUS PRESCALING The technique of dual-modulus prescaling is well established as a method of acheiving high performance frequency synthesizer operation at high frequencies. Basically, the approach allows relatively low-frequency programmable counters to be used as high-frequency programmable counters with speed capability of several hundred MHz. This is possible without the sacrifice in system resolution and performance that results if a fixed (single-modulus) divider is used for the prescaler. In dual-modulus prescaling, the lower speed counters must be uniquely configured. Special control logic is necessary to select the divide value P or P / 1 in the prescaler for the required amount of time (see modullus control definition). Lansdale's dual-modulus frequency synthesizers contain this feature and can be used with a variety of dual-modulus prescalers to allow speed, complexity and cost to be tailored to the system requirements. Prescalers having P, P / 1 divide values in the range of /3//4 to /128//129 can be controlled by most Lansdale frequency synthesizers. Several dual-modulus prescaler approaches suitable for use with the ML145146 are: ML12009 ML12011 ML12013 ML12015 ML12016 ML12017 ML12018 ML12032 /5//6 /8//9 /10//11 /32//33 /40//41 /64//65 /128//129 /64/65 or /128/129 440 MHz 500 MHz 500 MHz 225 MHz 225 MHz 225 MHz 520 MHz 1.1 GHz DESIGN GUIDELINES The system total divide value. Ntotal (NT) will be dictated by the application. i.e., N is the number programmed into the /N counter, A is the number programmed into the /A counter, P and P / 1 are the two selectable divide ratios available in the dual-modulus prescalers. To have a range of NT values in sequence, the /A counter is programmed from zero through P / 1 for a particular value N in the /N counter. N is then incremented to the N / 1, and the /A is sequenced from 0 through P / 1 again. There are minimum and maximum values that can be achieved for NT. These values are a function of P and the size of the /N and /A counters. The constraint N A always applies. If Amax = P - 1, then Nmin P - 1. Then NTmin = (P - 1) P + A or (P - 1)P since A is free to assume the value of 0. NTmax / Nmax * P + Amax To maximize system frequency capability, the dual-modulus prescaler output must go from low to high after each group of P or P - 1 input cycles. The prescaler should divide by P when its modulus control line is high and by P - 1 when the modulus control is low. For the maximum frequency into the prescaler (fVCOmax), the value used for P must be large enough such that: 1. fVCO max divided by P may not exceed the frequency capability of f in (input to the /N and /A counters). 2. The period of fVCO divided by P must be greater than the sum of the times: a. Propagation delay through the dual modulus prescaler. b. Prescaler setup or release time relative to its modulus control signal. c. Propagation time from f in to the modulus control output for the frequency synthesizer device. A sometimes useful simplification in the programming code can be achieved by choosing the values for P of 8, 16, 32, or 64. For these cases, the desired value of NT results when NT in binary is used as the program code to the /N and /A counters treated in the following manner: 1. Assume the /A counter contains "a" bits where 2aP. 2. Always program all higher order /A counter bits above "a" to 0 3. Assume the /N counter and the /A counter (with all the higher order bits above "a" ignored) combined into a single binary counter of n + a bits in length (n = number of divider stages in the /N counter). The MSB of this "hypothetical" counter is to correspond to the MSB of /N and the LSB is to correspond to the LSB of /A. The system divide value, NT, now results when the value of NT in binary is used to program the "new" n + a bit counter. By using the two devices, several dual-modulus values are achievable (shown in Figure 11). Page 9 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. APPLICATION MC The features of the ML145146 permit bus operation with a dedicated wire needed only for the strobe input. In a microprocessor-controlled system this strobe input is accessed when the phase lock loop is addressed. The remaining data and address inputs will directly interface to the microprocessor's data and address buses. The device architecture allows the user to establish any integer reference divide value between 3 and 4095. The wide selection of /R values permits a high degree of flexibility in choosing the reference oscillator frequency. As a result the reference oscillator can frequently be chosen to serve multiple system functions such as a second local oscillator in a receiver design or a microprocessor system clock. Typical applications that take advantage of these ML145146 features including the dual modulus capability are shown in Figures 12, 13 and 14. DEVICE A DEVICE B DEVICE B DEVICE A ML12009 /20//21 /50//51 /40//41 OR /80//81 ML12011 /32//33 /80//81 /64//65 OR /128//129 ML12013 /40//41 /100//101 /80//81 MC10131 MC10138 MC10154 NOTE: ML12009, ML12011 and ML12013 are pin equivalent. ML12015, ML12016 and ML12017 are pin equivalent. Figure 11. Dual Modulus Values Page 10 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. CHOICE OF REF. OSC. FREQUENCY (ON-CHIP OSC. OPTIONAL) 8 OSCout OSCin VDD ML145146 18 fR 15 fV 13 LD } 7 PDout 5 R 17 V 16 FOR USE WITH EXTERNAL PHASE DETECTOR (OPTIONAL) LOCK DETECT SIGNAL RECEIVER LO. 443.325 443.950 MHz (25 kHz STEPS) TRANSMITTER MODULATION AND 15.7 MHz TRANSMITTER SIGNAL OFFSET 459.025 - 459.650 MHz (25 kHz STEPS) 6 } LOOP FILTER CHOICE OF DETECTOR ERROR SIGNALS VCO 4 MOD 14 CONTROL VSS 3 fin D3 D2 D1 D0 A2 A1 A0 ST 19 20 1 2 11 10 9 12 CHIP SELECT TO CONTROLLER ML12034 PRESCALER TO SHARED CONTROLLER BUS NOTES: 1. Reciever I.F = 10.7 MHz, low side injection. 2. Duplex operation with 5 MHz receive/transmit separation. 3. fR = 25 kHz, + R chosen to correspond with desired reference oscillator frequency. 4. Ntotal = 17,733 to 17,758 = N * P + A; N = 227, A = 5 to 30 for P = 64. Figure 13. Synthesizer for UHF Mobil Radio Telephone Channels Demonstrates Use of the ML145146 in Microprocessor/Microcomputer Controlled Systems Operating to Several Hundred MHz CHOICE OF REF. OSC. FREQUENCY (ON-CHIP OSC. OPTIONAL) } X3 8 OSCout OSCin VDD ML145146 fR fV 5 LD PDout R 17 V 16 FOR USE WITH EXTERNAL PHASE DETECTOR (OPTIONAL) LOCK DETECT SIGNAL RECEIVER 2ND, L.O. 33,300 MHZ RECEIVER FIRST L.O. 825.030 844.980 MHZ (30 KHz STEPS) 7 6 } LOOP FILTER VCO X4 TRANSMITTER MODULATION X4 MOD 14 CONTROL 4 VSS fin 3 D3 D2 D1 D0 A2 A1 A0 ST 19 20 1 2 11 10 9 12 CHIP TO SHARED CONTROLLER BUS SELECT TO CONTROLLER CHOICE OF DETECTOR ERROR SIGNALS TRANSMITTER SIGNAL 825.030 844.880 MHz (30 kHz STEPS) MC10131 DUAL F/F ML12011 /8//9 PRESCALER +32/+32 DUAL MODULUS PRESCALER NOTES: 1. Receiver 1st I.F. = 45 MHz, low side injection; Receiver 2nd I.F. = 11.7 MHz, low side injection. 2. Duplex operation with 45 MHz receive/transmit separation. 3. fR = 7.5 kHz, + R = 1480. 4. Ntotal = N * 32 + A = 27,501 to 28,166: N = 859 to 880; A = 0 to 31. 5. Only one implementation is shown. Various other configurations and dual-modulus prescaling values to /128//129 are possible. Figure 14. 666 Channel, Computer Controlled, Mobile Radio Telephone Synthesizer for 800 MHz Cellular Radio Systems Page 11 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. OUTLINE DIMENSIONS SOG = -6P (MC145146-6P) CASE 751D-04 -A20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONA AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL, IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R INCHES MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 10.05 0.25 10.56 0.75 MILLIMETERS MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.020 0.035 .0395 0.010 0.415 0.029 -B- P 10 PL 0.25 (0.010) M B M 1 1 0 J 0.25 (0.010) M T B S A S F R X 45 C -TK M PLASTIC DIP (MC145146RP) CASE 738-03 -A20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982 2. CONTROLLING DIMENSION: INCH 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH INCHES MIN MAX 1.010 1.070 0.240 .0260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0.51 1.01 B 1 1 0 C L -TSEATING PLANE K M E G F D 20 PL 0.25 (0.010) M T A M N J 20 PL 0.25 (0.010) M T B M DIM A B C D E F G J K L M N Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. "Typical" parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc. Page 12 of 12 www.lansdale.com Issue 0 |
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